`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2019/11/10 17:25:41
// Design Name: 
// Module Name: Add_4bit_TOP
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module Add_4bit_TOP(
    input wire[3:0] A,
    input wire[3:0] B,
    input wire CCI,
    output wire[4:0] Y
    );
    
    Add_4bit_v3 add_4bit(
        .A3(A[3]),
        .A2(A[2]),
        .A1(A[1]),
        .A0(A[0]),
        .B3(B[3]),
        .B2(B[2]),
        .B1(B[1]),
        .B0(B[0]),
        .CI(CCI),
        .Y4(Y[4]),
        .Y3(Y[3]),
        .Y2(Y[2]),
        .Y1(Y[1]),
        .Y0(Y[0])
    );
    
endmodule
